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Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
FEATURES
* 9 LVHSTL outputs * Redundant differential CLK0, nCLK0 and CLK1, nCLK1 inputs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 500MHz * Output skew: 50ps (maximum) * Part-to-part skew: 250ps (maximum) * Propagation delay: 1.6ns (maximum) * VOH = 1V (maximum) * 3.3V core, 1.8V output operating supply voltages * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8521I-03 is a low skew, 1-to-9 Differential-to-LVHSTL Fanout Buffer and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8521I-03 has two selectable clock inputs. Redundant clock pairs, CLK0, nCLK0 and CLK1, nCLK1 can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output skew and part-to-part skew characteristics make the ICS8521I-03 ideal for today's most advanced applications, such as IA64 and static RAMs.
BLOCK DIAGRAM
CLK_EN CLK0 nCLK0 CLK1 nCLK1 CLK_SEL D Q LE 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8
PIN ASSIGNMENT
nQ0 Q0 VDDO VDDO nQ2 Q2 nQ1 Q1
32 31 30 29 28 27 26 25 VDD CLK0 nCLK0 CLK_SEL CLK1 nCLK1 GND CLK_EN 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO
ICS8521I-03
9 1 0 1 1 1 2 1 3 1 4 1 5 16
VDDO Q8 nQ8 Q7 nQ7 VDDO Q6 nQ6
32-Lead LQFP 7mm x 7mm x 1.4mm Package Body Y Package Top View
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Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Type Power Input Input Input Input Input Power Input Power Output Output Output Output Output Output Output Output Output Pullup Pulldown Pullup Pulldown Pulldown Pullup Description Core supply pin. Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0, nCLK0. LVTTL / LVCMOS interface levels. Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS /LVTTL interface levels. Output supply pins. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level. Differential output pair. LVHSTL interface level.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 17, 24, 25, 32 10, 11 12, 13 14, 15 18, 19 20, 21 22, 23 26, 27 28, 29 30, 31 Name VDD CLK0 nCLK0 CLK_SEL CLK1 nCLK1 GND CLK_EN VDDO nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Inputs Outputs Selected Sourced CLK0, nCLK0 CLK1, nCLK1 CLK0, nCLK0 Q0:Q8 Disabled; LOW Disabled; LOW Enabled nQ0:nQ8 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 CLK1, nCLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B.
Disabled
nCLK0, CLK1 CLK0, CLK1
Enabled
CLK_EN
nQ0:nQ8 Q0:Q8
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK0 or nCLK1 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q8 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ8 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels".
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Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDO IDD Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 95 Units V V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN CLK_SEL CLK_EN CLK_SEL VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLKx nCLKx CLKx nCLKx Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLKx and nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Test Conditions Minimum 0.7 0 0.4 Typical Maximum 1.0 0.4 1.0 Units V V V
TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle 266MHz 200 48 1.0 Test Conditions Minimum Typical Maximum 500 1.6 50 250 700 52 55 Units MHz ns ps ps ps % %
t sk(o) t sk(pp)
tR / tF odc
266MHz < 500MHz 45 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.8V 0.2V 3.3V 5% VDD
VDD VDDO
Qx
SCOPE
nCLK0, nCLK1
LVHSTL
nQx
V
CLK0, CLK1
PP
Cross Points
V
CMR
GND GND = 0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK0, nCLK1
80%
CLK0, CLK1 nQ0:nQ8 Q0:Q8
tPD
80% VSW I N G
Clock Outputs
20% tR tF
20%
PROPAGATION DELAY
nQ0:nQ8 Q0:Q8
OUTPUT RISE/FALL TIME
Pulse Width t
PERIOD
odc =
t PW t PERIOD
odc & tPERIOD
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REV. A APRIL 29, 2003
Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A APRIL 29, 2003
Integrated Circuit Systems, Inc. SCHEMATIC EXAMPLE
This application note provides general design guide using ICS8521I-03 LVHSTL buffer. Figure 3A shows a schematic example of the ICS8521I-03 LVHSTL Clock buffer. In this example,
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
the input is driven by an LVHSTL driver. CLK_EN is set at logic low to select CLK0/nCLK0 input.
Zo = 50 +
Zo = 50 VDDO=1.8V VDDO=1.8V C1 0.1u VDD=3.3V C5 0.1u 1.8V U1 32 31 30 29 28 27 26 25 C2 0.1u R2 50 C6 0.1u R1 50
-
Zo = 50 Ohm
Zo = 50 Ohm R12 1K LVHSTL Driv er R9 50 R10 50
1 2 3 4 5 6 7 8
VDDO Q0 nQ0 Q1 nQ1 Q2 nQ2 VDDO
VDD CLK0 nCLK0 CLK_SEL CL:K1 nCLK1 GND CLK_EN VDDO nQ8 Q8 nQ7 Q7 nQ6 Q6 VDDO
VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO
24 23 22 21 20 19 18 17
VDDO=1.8V
9 10 11 12 13 14 15 16 VDDO=1.8V C4 0.1u
ICS8521I-03
R11 VDD=3.3V
1K
C7 0.1u Zo = 50
C3 0.1u Zo = 50
+
-
R8 50
R7 50
FIGURE 3A. ICS8521I-03 SCHEMATIC EXAMPLE
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Integrated Circuit Systems, Inc. POWER, GROUND AND BYPASS CAPACITOR
This section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital IC. This layout guide is a general recommendation. The actual board design will depend on the component types being used, the board density and cost constraints. This description assumes that the board has clean power and ground planes. The goal is to minimize the ESR between the clean power/ground plane and the IC power/ground pin. A low ESR bypass capacitor should be used on each power pin. The value of bypass capacitors ranges from 0.01uF to 0.1uF. The bypass capacitors should be located
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
as close to the power pin as possible. It is preferable to locate the bypass capacitor on the same side as the IC. Figure 3B shows suggested capacitor placement. Placing the bypass capacitor on the same side as the IC allows the capacitor to have direct contact with the IC power pin. This can avoid any vias between the bypass capacitor and the IC power pins. The vias should be placed at the Power/Ground pads. There should be a minimum of one via per pin. Increasing the number of vias from the Power/Ground pads to Power/Ground planes can improve the conductivity
Zo = 50 +
Zo = 50 VDDO=1.8V VDDO=1.8V C1 0.1u VDD=3.3V C5 0.1u 1.8V Zo = 50 Ohm 1 2 3 4 5 6 7 8 U1 32 31 30 29 28 27 26 25 C2 0.1u R2 50 C6 0.1u R1 50
-
VDDO Q0 nQ0 Q1 nQ1 Q2 nQ2 VDDO
Zo = 50 Ohm R12 1K LVHSTL Driv er R9 50 R10 50
VDD CLK0 nCLK0 CLK_SEL CL:K1 nCLK1 GND CLK_EN VDDO nQ8 Q8 nQ7 Q7 nQ6 Q6 VDDO
VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO
24 23 22 21 20 19 18 17
VDDO=1.8V
9 10 11 12 13 14 15 16 VDDO=1.8V C4 0.1u
ICS8521I-03
R11 VDD=3.3V
1K
C7 0.1u Zo = 50
C3 0.1u Zo = 50
+
-
R8 50
R7 50
FIGURE 3B. RECOMMENDED LAYOUT
OF
BYPASS CAPACITOR PLACEMENT
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Integrated Circuit Systems, Inc. DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A APRIL 29, 2003
Integrated Circuit Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8521I-03. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8521I-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 32.8mW = 295.2mW
Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 295.2mW = 624.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.624W * 42.1C/W = 111.3C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT RL 50
FIGURE 5. LVHSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DDO_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (1.0V/50) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8521I-03 is: 944
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ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS8521I-03
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Marking ICS8521AYI-03 ICS8521AYI-03 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8521AYI-03 ICS8521AYI-03T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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